Voltage emergency prediction: Signature-based approach to reducing voltage emergencies

To reduce the gap between nominal and worst-case operating voltages, Harvard researchers have developed a “voltage emergency predictor” that identifies when emergencies are imminent and prevents their occurrence. A voltage emergency predictor anticipates voltage emergencies using “voltage emergency signatures” (the combination of control flow and microarchitectural events leadings up to them) and throttles machine execution to prevent them.

By doing so, the predictor enables chip designers to maximize performance with more aggressive timing margins. The signature-based predictor outperforms previously proposed architecture-centric techniques that rely only on voltage sensors to detect imminent problems and then react to emergencies via throttling. The invention recognizes and tracks patterns of emergency-prone activity to proactively throttle execution well before an emergency can occur.

High prediction accuracy is possible, which translates to performance enhancements by reducing otherwise conservative margins. Additionally, the voltage emergency predictor is trained during normal operation and does not require fine tuning based on specifics of the microarchitecture nor the power delivery subsystem, as is the case with reactive sensor-based schemes.


The potential market for this technology is manufacturers of semiconductor chips.

Power-constrained CMOS designs are making it increasingly difficult for microprocessor designers to cope with power supply noise. As current draw increases and operating voltage decreases, inductive noise threatens the robustness and limits the clock frequency of high-performance processors. Large current swings over small time scales cause large voltage swings in the power-delivery subsystem. A significant drop in supply voltage can cause timing margin violations by slowing down logic circuits. For reliable and correct operation of the processor, voltage emergencies - large voltage swings that violate noise margins - must be avoided. The traditional way to deal with inductive noise is to over-design the processor to tolerate worst-case fluctuations. Unfortunately, the gap between nominal and worst-case operating conditions in modern microprocessor designs is growing. Such conservative operating margins ensure robust operation of the system, but can severely degrade performance due to the lower operating frequencies.

U.S. Patent(s) Issued: US8949666B2