Increased system performance in multi-core computing systems


This invention describes an architectural enhancement to computing systems to greatly improve performance. A major performance bottleneck exists in multi-core processors, which are the dominant CPU architecture in servers, desktop computers and mobile devices. Compilers are available to exploit multi-core architectures, but overall system performance is limited by the communications latency between processing elements. This invention describes a ring cache that bypasses general purpose interconnects that are currently used and doubles system performance.

U.S. Patent(s) Issued: US10949200B2