Asynchronous circuit techniques for memory error correction

This invention describes a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More specifically, it involves the design of an error-correcting circuit (ECC) as applied to high density and low latency memories, especially NOR Flash and DRAM. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, memory cells are subject to higher rates of manufacturing defects and soft errors. Correction or manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.


This invention has the potential to reduce the costs of detecting manufacturing defects and requires minimal hardware complexity to implement. For use with any digital memory or digital communication channels.

U.S. Patent(s) Issued: US7546517B2